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Xilinx 12.4 License 19



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Xilinx 12.4 License 19


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Berkeley DB, used as a database in certain packages, is dual-licensed under GNUAGPLv3/Sleepycat licenses. Because service vendors that redistribute ourpackages could find packages with these licenses potentially detrimental totheir solutions, we have decided to remove Berkeley DB as a dependency fromthese packages. In the long term, SUSE aims to provide a solution withoutBerkeley DB.


This SUSE product includes materials licensed to SUSE under the GNUGeneral Public License (GPL).The GPL requires SUSE to provide the source code that corresponds to theGPL-licensed material.The source code is available for download at on Medium 2.For up to three years after distribution of the SUSE product, upon request, SUSE will mail a copy of the source code.Send requests by e-mail to sle_source_request@suse.com.SUSE may charge a reasonable fee to recover distribution costs.


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This release notes document is licensed under a Creative Commons Attribution-NoDerivatives 4.0 International License (CC-BY-ND-4.0). You should have received a copy of the license along with this document. If not, see -nd/4.0/.


Please if you are using this core, report if the marked bugs (CPHA='1', bit alignment) are solved for your toolchain. You can send me e-mail to jdoin@opencores.orgI have confirmation from people using Xilinx ISE 13.1, 12.4 and 12.1 with WebPack, Altium + ISE 12.3, Synopsys and Altera tools. I would like to know if the VHDL style used in this core works for your toolchain, and if not, what seems to be the problem. My goal is to find a description style that is as friendly as possible to synthesis tools. The scope screens below show a CPOL=1, CPHA=1 spi transaction. Debug signals show the slave internal state and slave flow control signals for the read/write ports. The spi_master and spi_slave cores are verified in FPGA hardware at 100MHz (50MHz spi clock) with 0 ns of SCK-to-MOSI delay and less than 2ns of SCK-to-MISO delay.In the example, the slave is used with wren_i permanently tied to HIGH. The parallel input data is sampled from di_i at start of transmission, until the first SPI SCK edge. For continuous transfers, the data at di_i is sampled again every falling edge on state 1. The scope screens below show 2 examples of continuous transfers: for CPOL=1, CPHA=0 and CPOL=0, CPHA=0 spi modes. The words are loaded when 'di_req' line goes to '1'. Data is presented to the port di_i and wren_i is pulsed to write the data word. In the screen on the right, the 1st 'di_req' data request (requesting data for the second word) is ignored by the slave parallel interface driver, and MISO is cleared (others => '0') for that word. The 3rd word is loaded normally ('wren' is strobed in time for the transfer).


This project started from the need to have robust yet simple SPI interface cores written in VHDL to use in generic FPGA-to-device interfacing.The resulting cores generate small and efficient circuits, that operate from very slow SPI clocks up to over 50MHz SPI clocks.The project contains 2 independent cores: SPI_MASTER and SPI_SLAVE.Both cores are written in VHDL, with fully pipelined RTL architecture and separate clock domains for the SPI bus clock and parallel I/O interface.The design is originally targeted to a Spartan-6 device, but is written in fully synthesizable, technology-independent VHDL.The circuits preserve FPGA clock resources by directly using the system high speed clock for all flops, with clock enables (CE) to clock registers.The master and slave cores were verified in hardware using the Digilent Atlys board (Spartan-6 @100MHz) with spi clocks from 500kHz to 50MHz SPI clock, with perfect phasing and very robust operation.If you find these cores useful, please let me know: jdoin@opencores.orgIf you find the LGPL license to be unfit for your purposes, please let me know and we can change the license for another open-source hardware license that can be integrated in your application.


Core Specifics Supported Family Spartan Virtex Device Tested S40-3 V300-4 CLBs 260 2442 Clock IOBs IOBs1 19 Performance (MHz) 12.4 MHz 34 MHz Xilinx Core Tools M1.3 M1.5i Special Features None Provided with Core Documentation Core Design Document Design File Formats EDIF netlist,.ngd, Verilog Source RTL available extra Constraints File m8254.ucf Verification Test vectors Instantiation Templates VHDL, Verilog Reference Designs None & Application Notes Additional Items None Simulation Tool Used Verilog XL, version 2.6 Support provided by Virtual IP Group Inc.


This AllianceCORE product is available from Xilinx AllianceCORE partner, Virtual IP Group, Inc., under terms of the SignOnce IP License. To learn about the SignOnce IP License program, contact Virtual IP Group, visit www.xilinx.com/ipcenter/signonce.htm, or write to commonlicense@xilinx.com. Please contact Virtual IP Group, Inc. for pricing and additional information about this AllianceCORE product.


For information on Xilinx programmable logic or development system software, contact your local Xilinx sales office, or: Xilinx, Inc. 2100 Logic Drive San Jose, CA 95124 Phone: +1 408-559-7778 Fax: +1 408-559-7114 URL: www.xilinx.com For general Xilinx literature, contact: Phone: E-mail: +1 800-231-3386 (inside the US) +1 408-879-5017 (outside the US) literature@xilinx.com


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